This application claims priority to Ser. No. 99400556.9, filed in Europe on Mar. 8, 1999 (TI-27760EU) and Ser. No. 98402455.4, filed in Europe on Oct. 6, 1998 (TI-28433EU).
The present invention relates to processors, and to management of a stack for passing variables during the execution of instructions in such processors.
Microprocessors are general purpose processors which require high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. It is known to provide a stack that can be used to pass variables from one software routine to another. Stacks are also used to maintain the contents of the program counter when a first software routine calls a second software routine, so that program flow can return to the first software routine upon completion of the called second routine. A call within the second software routine can call a third routine, etc.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in, but not exclusively, applications such as mobile telecommunications applications, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
One way of providing improved performance is to provide a larger instruction memory and to increase the length of the program counter so that the larger instruction memory can be directly addressed. However, this may result in program incompatibility between different generations of microprocessors.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of processors, such as for example, but not exclusively, digital signal processors.
In accordance with a first aspect of the invention, there is provided a processor that is a programmable digital signal processor (DSP), offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit, and a data computation unit for executing the instructions decoded by the instruction buffer unit. A program counter, which has a lower program counter portion and an upper program counter portion, provides an instruction address that is provided to the instruction memory. A first stack pointer is operable to address a first stack region in a data memory for saving a lower program counter value in response to an instruction, for example a CALL instruction, being executed by the microprocessor. A second stack pointer is operable to address a second stack region in the data memory for saving an upper program counter value in response to executing the CALL instruction. Advantageously, this preserves software code compatibility from an earlier generation microprocessor that passes variables via a stack.
In accordance with another aspect of the present invention, the data computation unit is operable to store a first variable value in the first stack region adjacent to the lower program counter value using a stack pointer relative address relative to the first stack pointer in response to executing another instruction, such as a PUSH instruction for example. Advantageously, the stack pointer relative address is not affected by the upper program counter value that is stored in the second stack region.
In accordance with another aspect of the present invention, a method of operating a digital system is provided. A plurality of instructions are executed in an improved processor core, wherein the instructions are fetched in response to a program counter from an instruction memory associated with the processor core. A first stack region is formed for holding a plurality of data values in a data memory associated with the processor core by maintaining a first stack pointer. A second stack region is formed separate from the first stack region in the data region for storing a second plurality of data values by maintaining a second stack pointer. A lower program counter value is stored in the first stack region in response to an instruction, such as a CALL, being executed in the data computation unit. A first upper program counter value is stored in the second stack region in response to executing the CALL instruction. A first argument value is then stored in the first stack region adjacent to the first lower program counter value using a stack pointer relative address relative to the first stack pointer in response to executing an instruction, such as a PUSH instruction for example. Advantageously, the stack pointer relative address is not affected by the upper program counter value that is stored in the second stack region, so that software code from a prior generation microprocessor can be easily ported to the improved microprocessor.
Another aspect of the present invention is that a context data value can be stored adjacent to the upper program counter value using a stack pointer relative address relative to the second stack pointer in response to executing the PUSH instruction. Advantageously, stack pointer relative addressing in the first stack region is not affected by the context data value that is stored in the second stack region. Thus, software code compatibility can be maintained while saving additional context information for added functionality.